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The Art of Timing Closure


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Table of Contents

Chapter 1. Introduction.- Chapter 2. Design Implementation Data Structures and Settings.- Chapter 3. Design Constraints Development.- Chapter 4. Multiple Modes and Multiple Corners Development.- Chapter 5. Concurrent Floor Planning and Placement.- Chapter 6. Placement and Timing Analysis.- Chapter 7. Clock Tree Synthesis and Timing Analysis.- Chapter 8. Detail Route and Timing, Power Analysis.- Chapter 9. Final Route and Timing Closure in all Modes and Corners.- Chapter 10. Functional and Physical Verification.

About the Author

Khosrow Golshan was Division Director at Conexant System Inc. and Technical Director at Synaptics Inc. while managing and directing worldwide ASIC design implementation and standard cell and I/O library development for various silicon process nodes. Prior to that he was Group Technical Staff at Texas Instrument’s R&D and Process Development Laboratory  responsible for processing silicon test-chip design and digital/mixed-signal ASIC development. He has over twenty years’ experience in ASIC design implementation methodology, flow development, and digital ASIC libraries design.

He is the author of Physical Design Essentials—An ASIC Design Implementation Perspective. In addition, he has published many technical articles and has held several US patents.

The author has earned advanced degrees in the areas of Electrical Engineering(West Coast University, Los Angeles, CA. Engineering Dept.), Applied Mathematics(Southern Methodist University, Dallas, TX. Mathematics Dept.) and a Bachelor of Science in Electronic Engineering(DeVry University, Dallas, TX. Engineering Dept.). He is also an IEEE life member.

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