Table of Contents

1. 3D thin-body FinFET and GAA: From device to compact model
2. Compact models for analog and RF applications
3. Core model for FinFETs
4. Gate-all-around FETs
5. Channel current and real device effects
6. Leakage currents
7. Charge, capacitance, and nonquasi-static effects
8. Parasitic resistances and capacitances
9. Noise
10. Junction diode I-V and C-V models
11. Benchmark tests for compact models
12. BSIM-CMG model parameter extraction
13. Temperature dependence
14. Cryogenic temperature modeling

About the Author

Yogesh Singh Chauhan is a Chair Professor in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, nanosheet/gate-all-around FETs, FDSOI transistors, negative capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.

Chenming Hu is TSMC Distinguished Chair Professor Emeritus at the University of California Berkeley, United States. He was the Chief Technology Officer of TSMC. He received the US Presidential Medal of Technology and Innovation from Pres. Barack Obama for developing the first 3D thin-body transistor FinFET, MOSFET reliability models and leading the development of BSIM industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. He received the highest honor of IEEE, the IEEE Medal of Honor, and its Andrew Grove Award, Solid Circuits Award, and the Nishizawa Medal. He also received the Taiwan Presidential Science Prize and UC Berkeley’s highest honor for teaching – the Berkeley Distinguished Teaching Award.

Sayeef Salahuddin is the TSMC Distinguished Chair Professor at the University of California, Berkeley He received the Presidential Early Career Award for Scientists and Engineers by President Obama among several other early career awards from multiple federal agencies. He also received the IEEE Andrew S Grove Award for his pioneering work in ferroelectric negative capacitance and its incorporation into the most advanced DRAM memory and back-end capacitors. He is a Fellow of the IEEE, APS and AAAS and is the editor-in-chief of the IEEE Electron Devices Letters.

Girish Pahwa is an assistant professor at the International College of Semiconductor Technology at National Yang Ming Chiao Tung University. Girish’s research primarily focuses on the modeling, simulation, and device-circuit co-design of upcoming and emerging nanoscale technologies.

Before his current role, Girish held multiple positions in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley including assistant professional researcher, postdoctoral scholar, and research and development engineer. He also served as the inaugural executive director of the Berkeley Device Modeling Center (BDMC) and made significant contributions to the BSIM suite of compact models. His notable works include the development of industry-focused compact models for cryogenic CMOS operation, ferroelectric devices, high-voltage MOSFETs, and thin film transistors.

Girish has received several prestigious awards, including the IEEE EDS Early Career Award (2022), the Outstanding Ph.D. Thesis Award from IIT Kanpur (2020), and the Best Paper Award at the IEEE International Conference on Emerging Electronics (2016). He is an active member of the IEEE EDS Compact Modeling Committee and the IEEE EDS Electronic Materials Committee. He has served as a reviewer for several journals and conferences and has been part of the technical program committee for the IEEE Electron Devices Technology and Manufacturing (EDTM) conference.

Girish earned his Ph.D. and master’s degrees in electrical engineering from the Indian Institute of Technology (IIT) Kanpur and his bachelor’s degree in electronics and communication engineering from Delhi Technological University.

Avirup Dasgupta is a faculty member in the Dept. of Electronics and Communication Engineering at the Indian Institute of Technology Roorkee (IITR), where he leads the DiRac Lab. His work primarily involves semiconductor physics, modeling and design of semiconductor devices and EDA. Prof. Dasgupta is a co-developer of multiple industry standard models including BSIM-BULK, BSIM-IMG, BSIM-CMG, BSIM-SOI and ASM-HEMT. He also develops various compact models for different industry clients. Prof. Dasgupta is an IEEE Senior Member and the recipient of multiple awards including the IEEE EDS Early Career Award (2021). He has served as the reviewer for multiple journals and conferences and serves as a member of the IEEE EDS Compact Modeling Technical Committee, IEEE EDS Publications and Products Standing Committee and IEEE UP Section Executive Committee.

Prof. Dasgupta completed his undergraduate, graduate and doctoral work at the Indian Institute of Technology Kanpur (IITK). He worked as the manager of the Berkeley Device Modeling Center (BDMC) and as a postdoctoral scholar in the BSIM group at the Dept. of Electrical Engineering and Computer Science, University of California Berkeley, prior to joining IITR.

Darsen D. Lu was one of the key contributors of the industry standard FinFET compact model, BSIM-CMG, and thin-body SOI compact model, BSIM-IMG. He received his B.Sc. in electrical engineering in 2005, from National Tsing Hua University, Hsinchu, Taiwan, and his M.Sc. and Ph.D. in electrical engineering from the University of California, Berkeley, in 2007 and 2011 respectively. From 2011 to 2015, he has been a research scientist at the IBM Thomas J. Watson Research Center, Yorktown Heights, New York. He is currently a Macronix Endowed Chair (Associate) Professor at National Cheng Kung University, Tainan, Taiwan. His current research focuses on the fabrication and modeling of ferroelectric memory (ferroelectric FinFET) devices, cryogenic CMOS modeling for high-performance and quantum computation, and the design of AI/neuromorphic circuits and systems.

Sriramkumar Venugopalan received his M.Sc. and Ph.D. in electrical engineering at the University of California, Berkeley and his B.Sc. from the Indian Institute of Technology (IIT), Kanpur. While pursuing his doctoral degree he contributed to research and development of multi-gate transistor compact SPICE models. He lead the industry standardization effort for BSIM-CMG model representing the BSIM Group at the Compact Model Council. He was the recipient of Outstanding Researcher Award from TSMC for his contributions to multi-gate SPICE models. He has authored and co- authored more than 30 research papers in the area of semiconductor device SPICE models and RF integrated circuit design. Dr. Venugopalan is currently leading wireless system design group at Skyworks Solutions, Inc. Prior to that he co-founded and was the CEO of RF Pixels, a 5G mmWave Radio startup which was later acquired by Skyworks. Dr. Venugopalan was also with Samsung Electronics pursuing RF integrated circuit design in advanced semiconductor technology nodes.

Ali M. Niknejad received his B.Sc in electrical engineering from the University of California, Los Angeles, in 1994, and his M.Sc. and Ph.D., also in electrical engineer- ing, from the University of California, Berkeley, in 1997 and 2000 respectively. He is currently a professor in the EECS department at UC Berkeley and Faculty Director of the Berkeley Wireless Research Center (BWRC) Group. He is also the Associate Director of the Center for Ubiquitous Connectivity (CUbiC) and also served as the Associate Director for the Center for Converged TeraHertz Communications and Sensing (ComSenTer). Prof. Niknejad received the 2020 SIA/SRC University Research Award, recognized “for noteworthy achievements that have advanced analog, RF, and mm-wave circuit design and modeling, which serve as the foundation of 5G+ technologies.” Professor Niknejad was the recipient of the 2012 ASEE Frederick Emmons Terman Award for his work and textbook on electromagnetics and RF integrated circuits. He has co-authored over 400 conference and journal publications in the field of integrated circuits and device compact modeling. His focus areas of research include analog, RF, mixed-signal, mm-wave circuits, device physics and compact modeling, and numerical techniques in electromagnetics.

Sourabh Khandelwal is an Associate Professor at Macquarie University. He is the lead author of two industry standard compact models: ASM-HEMT for GaN RF and power technology, and ASM-ESD for silicon ESD applications. He has also co-authored BSIM-CMG, BSIM-IMG and BSIM6 compact models during his tenure at the BSIM group at the University of California Berkeley. Dr Khandelwal has published 3 books and over 150 research papers. He regularly serves as consultant to multi-national semiconductor companies.

Juan Pablo Duarte Sepúlveda obtained his Ph.D. at the University of California, Berkeley in 2018. He received his B.Sc. in 2010 and his M.Sc. in 2012, both in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST). He held a position as a lecturer at the Universidad Tecnica Federico Santa Maria, Valparaiso, Chile, in 2012. He has authored many papers on nanoscale semiconductor device modeling and characterization. He received the Best Student Paper Award at the 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) for the paper: Unified FinFET Compact Model: Modelling Trapezoidal Triple-Gate FinFETs.

Navid Paydavosi is a seasoned hardware engineer with a decade of experience in advanced Si process technology and GPU and memory subsystem optimization. He excels in optimizing PPAC for complex SoC systems. He holds a Ph.D. in Electrical Engineering from the University of Alberta and completed a postdoctoral scholarship at UC Berkeley under supervision of Prof. Chenming Hu, contributing to the development of FinFET and SOI SPICE compact models. Navid began his Intel career in 2014 as a Logic Technology Development Device Engineer, where he contributed to key advancements in Intel 4 and Intel 3 technology nodes. He then served as a GPU Micro-Arch Power Optimization Engineer, leading innovations such as a novel Glitch minimization algorithm. As a NAND Flash Power and Performance Optimization Engineer, Navid significantly improved the power and performance of Intel's 3D NAND Flash products. Currently, he is a Senior Staff Intel Foundry Device Engineer, customizing the Intel 3 technology node for customers. Navid's expertise spans device physics, semiconductor manufacturing, and power optimization. His goal is to deliver world-class AI hardware solutions for Data Center and Edge computing environments.