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The Load-pull Method of RF and Microwave Power Amplifier Design
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Table of Contents

List of Figures xi

List of Tables xxi

Acronyms, Abbreviations, and Notation xxiii

Preface xxv

Foreword xxix

Biography xxxi

1 Historical Methods of RF Power Amplifier Design 1

1.1 The RF Power Amplifier 1

1.2 History of RF Power Amplifier Design Methods 3

1.2.1 Copper Tape and the X-Acto Knife 4

1.2.2 The Shunt Stub Tuner 4

1.2.3 The Cripps Method 5

1.3 The Load-Pull Method of RF Power Amplifier Design 5

1.3.1 History of the Load-Pull Method 6

1.3.2 RF Power Amplifier Design with the Load-Pull Method 8

1.4 Historical Limitations of the Load-Pull Method 9

1.4.1 Minimum Impedance Range 10

1.4.2 Independent Harmonic Tuning 11

1.4.3 Peak and RMS Power Capability 12

1.4.4 Operating and Modulation Bandwidth 12

1.4.5 Linearity Impairment 13

1.4.6 Rigorous Error Analysis 14

1.4.7 Acoustically Induced Vibrations 14

1.5 Closing Remarks 15

References 15

2 Automated Impedance Synthesis 17

2.1 Methods of Automated Impedance Synthesis 18

2.1.1 Passive Electromechanical Impedance Synthesis 18

2.1.2 The Active-Loop Method of Impedance Synthesis 21

2.1.3 The Active-Injection Method of Impedance Synthesis 24

2.2 Understanding Electromechanical Tuner Performance 26

2.2.1 Impedance Synthesis Range 26

2.2.2 Operating Bandwidth 27

2.2.3 Modulation Bandwidth 29

2.2.4 Tuner Insertion Loss 31

2.2.5 Power Capability 32

2.2.6 Vector Repeatability 34

2.2.7 Impedance State Resolution and Uniformity 35

2.2.8 Factors Influencing Tuner Speed 36

2.2.9 The Slab-Line to Coaxial Transition 37

2.3 Advanced Considerations in Impedance Synthesis 37

2.3.1 Independent Harmonic Impedance Synthesis 37

2.3.2 Sub-1 Impedance Synthesis 41

2.4 Closing Remarks 43

References 43

3 Load-Pull System Architecture and Verification 45

3.1 Load-Pull System Architecture 46

3.1.1 Load-Pull System Block Diagram 46

3.1.2 Source and Load Blocks 48

3.1.3 Signal Synthesis and Analysis 52

3.1.4 Large-Signal Input Impedance Measurement 53

3.1.5 AM-AM, AM-PM, and IM Phase Measurement 53

3.1.6 Dynamic Range Optimization 54

3.2 The DC Power Source 54

3.2.1 Charge Storage, Memory, and Video Bandwidth 55

3.2.2 Load-Pull of True PAE 56

3.2.3 The Effect of DC Bias Network Loss 57

3.3 The GT Method of System Verification 57

3.4 Electromechanical Tuner Calibration 60

3.5 Closing Remarks 60

References 61

4 Load-Pull Data Acquisition and Contour Generation 63

4.1 Constant Source Power Load-Pull 64

4.1.1 Load-Pull with a Single Set of Contours 65

4.1.2 Load-Pull with Two or More Sets of Contours 69

4.1.3 Load-Pull for Signal Quality Optimization 73

4.1.4 Large-Signal Input Impedance 76

4.2 Fixed-Parametric Load-Pull 77

4.2.1 Fixed Load Power 77

4.2.2 Fixed Gain Compression 79

4.2.3 Fixed Peak-Average Ratio 79

4.2.4 Fixed Signal Quality 80

4.2.5 Treating Multiple Contour Intersections 81

4.3 Harmonic Load-Pull 82

4.3.1 Second Harmonic Load-Pull 83

4.3.2 Third-Harmonic Load-Pull 85

4.3.3 Higher-Order Effects and Inter-harmonic Coupling 85

4.3.4 Baseband Load-Pull for Video Bandwidth Optimization 85

4.4 Swept Load-Pull 87

4.4.1 Swept Available Source Power 87

4.4.2 Swept Bias 88

4.4.3 Swept Frequency 88

4.5 Advanced Techniques of Data Acquisition 88

4.5.1 Simplified Geometric-Logical Search 89

4.5.2 Synthetic Geometric-Logical Search 89

4.5.3 Multidimensional Load-Pull and Data Slicing 91

4.5.4 Min-Max Peak Searching 93

4.6 Closing Remarks 94

References 95

5 Optimum Impedance Identification 97

5.1 Physical Interpretation of the Optimum Impedance 97

5.2 The Optimum Impedance Trajectory 99

5.2.1 Optimality Condition 99

5.2.2 Uniqueness Condition 100

5.2.3 Terminating Impedance 100

5.3 Graphical Extraction of the Optimum Impedance 101

5.3.1 Optimum Impedance State Extraction 101

5.3.2 Optimum Impedance Trajectory Extraction 102

5.3.3 Treatment of Orthogonal Contours 104

5.4 Optimum Impedance Extraction from Load-Pull Contours 105

5.4.1 Simultaneous Average Load Power and PAE 106

5.4.2 Simultaneous Average Load Power, PAE, and Signal Quality 107

5.4.3 Optimum Impedance Extraction Under Fixed-Parametric Load-Pull 108

5.4.4 PAE and Signal Quality Extraction Under Constant Average Load Power 109

5.4.5 Optimum Impedance Extraction with Bandwidth as a Constraint 110

5.4.6 Extension to Source-Pull 112

5.4.7 Extension to Harmonic and Base-Band Load-Pull 112

5.5 Closing Remarks 112

6 Matching Network Design with Load-Pull Data 115

6.1 Specification of Matching Network Performance 116

6.2 The Butterworth Impedance Matching Network 116

6.2.1 The Butterworth L-Section Prototype 117

6.2.2 Analytical Solution of the Butterworth Matching Network 119

6.2.3 Graphical Solution of the Butterworth Matching Network 120

6.3 Physical Implementation of the Butterworth Matching Network 121

6.3.1 The Lumped-Parameter Butterworth Matching Network 122

6.3.2 The Distributed-Parameter Butterworth Matching Network 124

6.3.3 The Hybrid-Parameter Butterworth Matching Network 126

6.4 Supplemental Matching Network Responses 130

6.4.1 The Chebyshev Response 131

6.4.2 The Hecken and Klopfenstein Responses 131

6.4.3 The Bessel-Thompson Response 135

6.5 Matching Network Loss 135

6.5.1 Definition of Matching Network Loss 135

6.5.2 The Effects of Matching Network Loss 136

6.5.3 Minimizing Matching Network Loss 137

6.6 Optimum Harmonic Termination Design 138

6.6.1 Optimally Engineered Waveforms 138

6.6.2 Physical Implementation of Optimum Harmonic Terminations 140

6.6.3 Optimum Harmonic Terminations in Practice 141

6.7 Closing Remarks 142

References 143

About the Author

DR. JOHN F. SEVIC has held design positions at Motorola, Qualcomm, Tropian, Cree, Maury Microwave, and Focus Microwave, and is currently at Maja Systems, where he is engaged in millimeter-wave antenna design. John is inventor of one of the most widely used methods of battery-life improvement for mobile phones, stochastic efficiency optimization, found in virtually all mobile phone platforms. He has served on the IEEE Microwave Theory and Techniques Editorial Review Board, IEEE IMS TPC, and IEEE ARFTG TPC. John is lead inventor of ten US patents, with several pending, and has a Ph.D., MS, and BS, all in electrical engineering.

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