Table of Contents

I Circuit Level Power Management.- 1 Comparative Analysis of Flip-Flops and Application of Data-Gating in Dynamic Flip-Flops for High Speed, Low Active and Low Leakage Power Dissipation.- 2 Low Power Sandwich/Spin Tunneling Memory Device.- II Architecture Level Power Management.- 3 Power-Efficient Issue Queue Design.- 4 Micro-Architecture Design and Control Speculation for Energy Reduction.- 5 Energy-Exposed Instruction Sets.- III Operating System Level Power Management.- 6 Dynamic Management of Power Consumption.- 7 Power Management Points in Power-Aware Real-Time Systems.- 8 A Power-Aware API for Embedded and Portable Systems.- IV Compiler Level Power Management.- 9 PACT HDL: A Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations.- 10 Compiler Optimizations for Low Power Systems.- 11 Power-Performance Trade-Offs in Second Level Memory Used by an ARM-like RISC Architecture.- V Application Level Power Management.- 12 Application-Level Power Awareness.- 13 A Power-Aware, Satellite-Based Parallel Signal Processing Scheme.- 14 The Case for Power Management in Web Servers.- VI Measurements and Evaluation.- 15 Et2: A Metric for Time and Energy Efficiency of Computation.- 16 Challenges for Architectural Level Power Modeling.- 17 Software Energy Profiling.